Article 5215

Title of the article

RISC ARITHMETIC LOGIC UNIT FOR CALCULATION OF MULTILEVEL ARRAYS

Authors

Fedyunin Roman Nikolaevich, Candidate of engineering sciences, associate professor, sub-department of computer engineering, Penza State University (40 Krasnaya street, Penza, Russia), frn_penza@mail.ru
Voynov Artem Sergeevich, Student, Penza State University (40 Krasnaya street, Penza, Russia), voj49@yandex.ru
Senokosov Il'ya Vladimirovich, Student, Penza State University (40 Krasnaya street, Penza, Russia), senokosov.i@yandex.ru

Index UDK

004.272.42

Abstract

Background. Working at the junction of several areas of mathematical and in-formation sciences gives results that are used in various applications, such as digital signal processing, cryptography etc. The elements of matrix algebra algorithms allow to create the algorithms of parallel and distributed processing of multidimensional arrays. Implementation on FPGA allows to quick and cheap testing hardware and software implementation of the mathematical apparatus.
Materials and methods. The research and implementation of RISC-core process-ing for multidimensional arrays were carried out on the basis of the formalism of the theory of nondeterministic automata, followed by functional simulation RISC-core CAD ALTERA QUARTUS. Algorithms of matrix algebra acted as the basic algo-rithms of units research and implementation.
Results. The article shows a detailed description of RISC-core processing for multidimensional arrays. The authors obtained a model of RISC-core functioning, based on the theory of non-deterministic automata, suggested a system of canonical equations based on the mathematical model of RISC-core and carried out a circuit implementation of the functional blocks of RISC-core, followed by modeling in CAD Altera Quartus.
Conclusions. The authors have proposed a method for implementation of the functional blocks of RISC-core to perform matrix algebra operation. The researchers used the theory of nondeterministic automata to implement a model of the functional blocks of the device. The authors carried out a mathematical description and then a functional simulation of devices at a soft-processor level.

Key words

RISC, soft-core, arithmetic logic unit, unit for multilevel arrays calculation, CAD Altera Quartus, matrix.

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References

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Дата создания: 02.10.2015 15:12
Дата обновления: 05.10.2015 09:17